1. Field of the Invention
The present invention relates to the field of memory cells which can be made in MOS technology.
More specifically, the present invention relates to a memory cell including a control gate and a floating gate in which the floating gate is arranged laterally with respect to the control gate.
2. Discussion of the Related Art
U.S. Pat. No. 5,687,113, issued to Constantin Papadas and Bernard Guillaumot, assigned to the present assignee and incorporated herein by reference, describes such a cell in which the floating gate is arranged laterally with respect to the control gate.
FIG. 1 shows a memory cell of the type of that described in the above-mentioned patent. The cell is formed in a single-crystal silicon substrate 1, more specifically in an active area of this substrate delimited by a thick oxide layer 2. The upper surface of the semiconductor substrate is coated with a thin silicon oxide layer 3 on which is formed a polysilicon control gate 4. The lateral walls of the polysilicon gate are insulated by a silicon oxide layer 5 and polysilicon spacers 7 and 8 are formed on either side of the gate. In the above-mentioned patent, conductive lateral spacers 7 and 8 are formed above respective source and drain extension areas 9 and 10. For example, if the substrate is of type P, the source and drain extensions are of type N. Further, the cell includes more heavily doped N.sup.+ -type source and drain areas 11 and 12.
Of course, the cell illustrated in FIG. 1 is not finished. To finish it, contacts need to be established with the source, drain, and control gate regions. The cell may include a single lateral spacer 8 above a drain extension.
The cell of this prior patent of the applicant provides satisfactory results. However, it is not compatible with all MOS integrated circuit manufacturing technologies and requires a double level of polysilicon layers, the first level corresponding to the control gate and the second level corresponding to a layer from which spacers 7 and 8 have been formed.